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Configuration Read (1010) and Write (1011)
The Configuration Read command is used to read the configuration space of each device. The Configuration Write
command is used to write information into the configuration space. The device is selected if its IDSEL signal is asserted
and AD[1:0] are set to '00'. Additional address bits are defined as follows:
? AD[7:2] contain one of 64 DWORD addresses for the configuration registers.
? AD[10:8] indicate which device of a multi-function agent is addressed. The core does not support multi-function
devices, and these bits should be '000'.
? AD[31:11] are ignored.
The core supports burst configuration read and write cycles.
Disconnects and Retries
The CorePCIF Target will perform either single-DWORD or burst transactions, depending on the request from the
system Master. If the backend is unable to deliver data quickly enough, the Target will respond with either a PCI retry or
disconnect, with or without data. If the system Master requests a transfer that the backend is not able to perform, a
Target abort can be initiated by the backend.
CorePCIF Master Function
The Master function in CorePCIF is designed to do the following:
? Arbitrate for the PCI bus
? Initiate a PCI cycle
? Pass dataflow control to the Target controller
? End the transfer when the DMA count has been exhausted
? Allow the backend hardware to stop and start DMA cycles
Master transfers can be initiated directly from the backend interface, or another PCI device may program the DMA
engine to initiate a PCI transfer.
Backend Interface
Through the backend interface (BE_REQ, BE_GNT, BE_ADDRESS, etc.), an external processor can access the
DMA Master control registers and initiate a Master transfer. This interface also allows the complete PCI configuration
space to be accessed so the core can be self-configured by a backend processor. This is required when the core is used to
implement the PCI device responsible for configuring the PCI bus. A hardware lock (BE_CFGLOCK) is provided for
safety reasons to prevent the backend from changing the values in the PCI configuration space.
Supported Master Commands
The CorePCIF Master controller is capable of performing configuration, I/O, memory, and interrupt acknowledge
cycles. Data transfers can be up to 2 32 bytes.
The Master controller will attempt to complete the transfer using a maximum-length PCI burst unless the maximum
burst length bits are set in the control register. If the addressed Target is unable to complete the transfer and performs a
retry or disconnect, the Master control will restart the transfer and continue from the last known good transfer. If a
Target does not respond (no DEVSELn asserted) or responds with a Target abort cycle, the Master controller will abort
the current transaction and report it as an error in the control register.
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相关PDF资料
COREU1LL-AR
IP MODULE COREU1LL
COREU1PHY-AR
IP MODULE COREU1PHY
CORR-8BIT-XM-UT2
SITE LICENSE IP CORRELATOR XP
CP2-GSA-L
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CP2-HSA110-1
CONN SHROUD CPCI 2MM TYPE A 22
CP2-HSC055-4
CONN SHROUD CPCI 2MM TYPE C 11
CP2-K3567-SR-F
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CP2105EK
KIT EVAL FOR CP2105
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